The present invention relates to a floating point processor and more particularly to a floating point processor which will perform floating point addition or subtraction on a pair of binary arguments utilizing serial arithmetic.
In pursuing ever greater computational power, increasing interest is being directed toward multiprocessor systems in which the total power of computation is increased by increasing the number of processors working on a given problem rather than merely increasing the size and speed of the processors themselves. As is understood, further increases in the speed and power of existing processor designs are very difficult to achieve and the costs are disproportionate to the improvements obtained. Further, speeds have currently reached a point where the length of even relatively short wires introduces delays which are difficult to compensate for. Similarly, while some multiprocessor systems proposed heretofore have utilized a bus structure for linking or coupling multiple processors and memory, the bandwidth or throughput of the bus has quickly become a factor limiting how far such designs may be expanded. Accordingly, attention has increasingly been shifting to multiprocessor architectures in which a multiplicity of processors communicate with a shared memory through a switching network which allows each processor to communicate with any portion of the memory. Known examples of this general type of multiprocessor architecture include the Butterfly computer manufactured and sold by Bolt Beranek and Newman Inc. of Cambridge, Massachusetts and the Connection Machine manufactured and sold by Thinking Machines, Inc. of Cambridqe, Mass. The architectures of the Butterfly computer and its switching network are described in BBN Report Nos. 3501 and 4098 (Chapter III) to the Defense Advanced Research Projects Agency (DARPA). The Connection Machine architecture is described in U. S. Pat. No. 4,598,400 issued July 1, 1986 to W. Daniel Hillis.
An improvement on the original Butterfly switching network is disclosed and claimed in copending, coassigned application Ser. No. 277,993 entitled "Memory Accessing Switch Network" and filed by Philip Carvey, William Crowther and Randall Rettberg. The disclosure of that application is incorporated herein by reference.
The switching network disclosed in application Ser. No. 277,993 establishes a system architecture in which a multiplicity of processors are synchronized to issue memory request messages at essentially the same predetermined time within a frame interval which encompasses a large number of basic clock periods. The messages are issued in a bit serial format in which the first part of the message comprises the memory address. In the switching network, the messages traverse a succession of layers of routing switch elements each of which makes routing decisions based on respective bits of the address so that each message is directed to the right memory module or address. The network architecture also includes concentrator elements which keep the number of leads required between layers within reasonable bounds. Further, the switch and concentrator elements include mechanisms for reducing contention between messages and for combining memory read operations so as to ameliorate the consequences of multiple processor attempting to read the same memory location.
While conventional microprocessors, i.e. processors utilizing parallel arithmetic, might be utilized for the multiple processors contemplated in application Ser. No. 277,993, e.g. by providing them with hardware or program code to format the desired bit serial messages, the full power of such processors would typically not be utilizable since the bit serial message format would typically introduce such a long delay in filling memory reuests that the processors would be held up by lack of data to process. Further, the costs, dictated mainly by the silicon chip area and power requirements of a multiplicity of such conventional parallel processors, would be onerous in attempting to construct systems employing a very large number of processors. Accordingly, it has been proposed to utilize processors which employ serial arithmetic. As in understood by those skilled in the art, serial arithmetic processors can be devised which utilize many fewer gate elements, i.e. less silicon area.
While serial arithmetic is not per se new, the present invention relates to novel apparatus for performing floating point addition and subtraction in a manner which is quite contrary to conventional wisdom and which results in a considerable saving in silicon area, in power consumption and in processing time.